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smsc emc2302 datasheet revision 1.3 (05-18-11) datasheet product features emc2302 dual rpm-based pwm fan controller general description the emc2302 is an smbus co mpliant fan controller with up to two independently controlled pwm fan drivers. each fan driver is cont rolled by a programmable frequency pwm driver and fan speed control algorithm that operates in either a closed loop fashion or as a directly pwm-controlled device. the closed loop fan speed control algorithm (fsc) has the capability to detect agi ng fans and alert the system. it will likewise detect stalled or locked fans and trigger an interrupt. additionally, the emc2302 offers a clock output so that multiple devices may be chained and slaved to the same clock source for optimal performance in large distributed systems. applications ? servers ? projectors ? industrial and networking equipment ? notebook computers features ? two programmable fan control circuits (emc2302) ? 4-wire fan compatible ? high speed pwm (26 khz) ? low speed pwm (9.5hz - 2240 hz) ? optional detection of aging fans ? fan spin up control and ramp rate control ? alert on fan stall ? watchdog timer ? rpm-based fan control algorithm ? 0.5% accuracy from 500 rpm to 16k rpm (external crystal oscillator) ? 1% accuracy from 500 rpm to 16k rpm (internal clock) ? smbus 2.0 compliant ? smbus alert compatible ? clk pin can provide a clock source output ? available in a 10-pin msop lead-free rohs compliant package block diagram smbus slave protocol pwm drivers smclk smdata tachometer limit registers tach measurement clk alert# fan speed control algorithm fan speed control algorithm tach1 tach2 pwm1 pwm2
order number(s): this product meets the halogen maximum concentration values per iec61249-2-21 for rohs compliance and environmen tal information, please visit www.smsc.com/rohs ordering number package features emc2302-1-aizl-tr 10-pi n msop (lead-free rohs compliant) two rpm-based fan speed control algorithms. smbus address 0101_110(r/w) EMC2302-2-AIZL-TR 10-pi n msop (lead-free rohs compliant) two rpm-based fan speed control algorithms. smbus address 0101_111(r/w) dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 2 smsc emc2302 datasheet 80 arkay drive, hauppauge, ny 11788 (631) 435-6000 or 1 (800) 443-semi copyright ? 2011 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc produc ts are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and produc t descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this inform ation does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporat ion (?smsc?). product names and company na mes are the trademarks of their respective holders. smsc disclaims and excludes any and all warrant ies, including without limi tation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, a nd against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of wa rranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages.
dual rpm-based pwm fan controller datasheet smsc emc2302 3 revision 1.3 (05-18-11) datasheet table of contents chapter 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 chapter 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 smbus electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 chapter 3 communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 system management bus interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.1 smbus start bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.2 smbus address and rd / wr bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.3 smbus data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.4 smbus ack and nack bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.5 smbus stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.6 smbus time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.7 smbus and i 2 c compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 smbus protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1 write byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.2 read byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.3 send byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.4 receive byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.5 block write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.6 block read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.7 alert response address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 chapter 4 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 fan control modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 pwm fan driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 rpm-based fan speed control algorithm (fsc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.1 programming the rpm-based fan speed control algo rithm . . . . . . . . . . . . . . . . . . . . . 18 4.4 tachometer measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4.1 stalled fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4.2 aging fan or invalid drive detectio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 clk pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.1 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.2 internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 spin up routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.7 ramp rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.8 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.8.1 power up operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.8.2 continuous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 chapter 5 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 lock entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 fan status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.1 fan status - 24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.2 fan stall status - 25h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.3 fan spin status - 26h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.4 fan drive fail status - 27h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 4 smsc emc2302 datasheet 5.4 fan interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5 pwm configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.5.1 pwm polarity config - 2ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.5.2 pwm output config - 2bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6 pwm base frequency register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.7 fan setting registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.8 pwm divide registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.9 fan configuration 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.10 fan configuration 2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.11 gain registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.12 fan spin up configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.13 fan max step registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.14 fan minimum drive registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.15 valid tach count registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.16 fan drive fail band registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.17 tach target registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.18 tach reading registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.19 software lock register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.20 product id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.21 manufacturer id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.22 revision register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 chapter 6 typical operating curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 chapter 7 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.1 emc2302 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2 package markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 chapter 8 datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
dual rpm-based pwm fan controller datasheet smsc emc2302 5 revision 1.3 (05-18-11) datasheet list of figures figure 1.1 emc2302 pin diagram (10-pin msop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3.1 smbus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4.1 system diagram of emc2 302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4.2 spin up routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4.3 ramp rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7.1 emc2302 package drawing - 10-pin msop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 7.2 emc2302 package markings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 6 smsc emc2302 datasheet list of tables table 1.1 pin description for emc2302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 1.2 pin types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2.2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2.3 smbus electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3.1 protocol format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3.2 write byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3.3 read byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3.4 send byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3.5 receive byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3.6 block write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3.7 block read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3.8 alert response address protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4.1 fan controls active for operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5.1 emc2302 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5.2 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5.3 fan status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5.4 fan interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5.5 pwm configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5.6 pwm base frequency register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5.7 pwm_basex[1:0] bit decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5.8 fan driver setting registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5.9 pwm divide registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5.10 fan configuration 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5.11 range decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5.12 minimum edges for fan ro tation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5.13 update time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5.14 fan configuration 2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 5.15 derivative options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 5.16 error range options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5.17 gain registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5.18 gain decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5.19 fan spin up configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 5.20 drive_fail_cnt[1:0] bit decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 5.21 spin level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.22 spin time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.23 fan max step registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.24 minimum fan drive registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 5.25 valid tach count registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 5.26 fan drive fail band registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5.27 tach target registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5.28 tach reading registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 5.29 software lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5.30 product id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5.31 manufacturer id register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.32 revision register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 8.1 customer revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
dual rpm-based pwm fan controller datasheet smsc emc2302 7 revision 1.3 (05-18-11) datasheet chapter 1 pin description figure 1.1 emc2302 pin diagram (10-pin msop) table 1.1 pin description for emc2302 pin number pin name pi n function pin type 1smdata smbus data input/output - requires external pull-up resistor diod (5v) 2smclk smbus clock input - requires external pull-up resistor di (5v) 3 vdd power supply power 4 gnd ground power 5pwm1 push-pull pwm output driver for fan 1 do open drain pwm output driver for fan 1 od (5v) 6tach1 open drain tachometer input for fan 1- requires pull-up resistor di (5v) 7pwm2 push-pull pwm output driver for fan 2 do open drain pwm output driver for fan 2 od (5v) 8tach2 open drain tachometer input for fan 2 - requires pull-up resistor di (5v) emc2302 10-msop 1 2 3 10 9 8 vdd smclk pwm1 smdata clk gnd tach1 pwm2 tach2 alert# 4 5 7 6
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 8 smsc emc2302 datasheet the pin types are described in detail below. all pins labeled with (5v) are 5v tolerant. application note: for the 5v tolerant pins that have a pull-up resistor, the voltage difference between vdd and the 5v tolerant pad must never be more than 3.6v. 9clk clock input for tachometer measurement di (5v) push pull clock output to other fan controllers to synchronize fan speed control do 10 alert# active low interrupt - requires external pull-up resistor. od (5v) table 1.2 pin types pin type description power this pin is used to supply power or ground to the device. di digital input - this pin is used as a digital input. this pin is 5v tolerant. do push / pull digital output - this pin is used as a digital output. it can both source and sink current. diod digital input / open drain output this pin is used as a digital i/o. when it is used as an output, it is open drain and requires a pull-up resistor. this pin is 5v tolerant. od open drain digital output - this pin is used as a digital output. it is open drain and requires a pull-up resistor. this pin is 5v tolerant. table 1.1 pin description for emc2302 (continued) pin number pin name pi n function pin type
dual rpm-based pwm fan controller datasheet smsc emc2302 9 revision 1.3 (05-18-11) datasheet chapter 2 electrical specifications note: stresses above those listed could cause permane nt damage to the device. this is a stress rating only and functional operation of the devic e at any other condition above those indicated in the operation sections of this specification is not implied. note 2.1 for the 5v tolerant pins that have a pull-up resistor, the pull-up voltage must not exceed 3.6v when the emc2302 is unpowered. 2.1 electrical specifications table 2.1 absolute maximum ratings voltage on 5v tolerant pins ( v 5vt_pin ) -0.3 to 5.5 v voltage on 5v tolerant pins ( |v 5vt_pin - v dd | ) (see note 2.1 )0 to 3.6 v voltage on vdd pin -0.3 to 4 v voltage on any other pin to gnd -0.3 to vdd + 0.3 v package thermal restance - junction to ambient ( ja ) 132 c/w operating ambient temperature range -40 to 125 c storage temperature range -55 to 150 c esd rating, all pins, hbm 2000 v table 2.2 electrical specifications v dd = 3v to 3.6v, t a = -40c to 125c, all typical values at t a = 27c unless otherwise noted. characteristic symbol min typ max unit conditions dc power supply voltage v dd 33.33.6v supply current i dd 400 550 ua pwm fan driver pwm resolution pwm 256 steps pwm duty cycle duty 0 100 % rpm-based fan controller tachometer range tach 480 16000 rpm tachometer setting accuracy tach 0.5 1 % external oscillator 32.768khz tach 1 2 % internal oscillator input high voltage v ih 2.0 v
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 10 smsc emc2302 datasheet note 2.2 all voltages are relative to ground. 2.2 smbus electrical specifications input low voltage v il 0.8 v output high voltage v oh vdd - 0.4 v 8 ma current drive output low voltage v ol 0.4 v 8 ma current sink leakage current i leak 5 ua alert# pin powered and unpowered 0c < ta < 85c pull-up voltage < 3.6v table 2.3 smbus electrical specifications vdd= 3v to 3.6v, t a = -40c to 125c typical values are at t a = 27c unless otherwise noted. characteristic symbol min typ max units conditions smbus interface input high voltage v ih 2.0 v input low voltage v il 0.8 v output high voltage v oh vdd - 0.4 v output low voltage v ol 0.4 v 4 ma current sink input high/low current i ih / i il 5 ua powered and unpowered 0c < ta < 85c input capacitance c in 5pf smbus timing clock frequency f smb 10 400 khz spike suppression t sp 50 ns bus free time start to stop t buf 1.3 us setup time: start t su:sta 0.6 us setup time: stop t su:stp 0.6 us data hold time t hd:dat 0us data setup time t su:dat 0.6 us table 2.2 electrical specifications (continued) v dd = 3v to 3.6v, t a = -40c to 125c, all typical values at t a = 27c unless otherwise noted. characteristic symbol min typ max unit conditions
dual rpm-based pwm fan controller datasheet smsc emc2302 11 revision 1.3 (05-18-11) datasheet clock low period t low 1.3 us clock high period t high 0.6 us clock/data fall time t fall 300 ns min = 20+0.1c load ns clock/data rise time t rise 300 ns min = 20+0.1c load ns capacitive load c load 400 pf per bus line table 2.3 smbus electrical specifications (continued) vdd= 3v to 3.6v, t a = -40c to 125c typical values are at t a = 27c unless otherwise noted. characteristic symbol min typ max units conditions
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 12 smsc emc2302 datasheet chapter 3 communications 3.1 system management bus interface protocol the emc2302 communicates with a host controller, su ch as an smsc sio, through the smbus. the smbus is a two-wire serial communication prot ocol between a computer host and its peripheral devices. a detailed timing diagram is shown in figure 3.1 . stretching of the smclk signal is supported; however, the emc2302 will not stretch the clock signal. 3.1.1 smbus start bit the smbus start bit is defined as a transition of th e smbus data line from a logic ?1? state to a logic ?0? state while the smbus clock line is in a logic ?1? state. 3.1.2 smbus address and rd / wr bit the smbus address byte consists of the 7-bit client address followed by a rd / wr indicator bit. if this rd / wr bit is a logic ?0?, then the smbus host is wr iting data to the client device. if this rd / wr bit is a logic ?1?, then the smbus host is reading data from the client device. the emc2302-1 smbus address is set at 0101_110(r/w)b. the emc2302-2 smbus address is set at 0101_111(r/w)b. 3.1.3 smbus data bytes all smbus data bytes are sent most significant bit first and composed of 8-bits of information. 3.1.4 smbus ack and nack bits the smbus client will acknowledge all data bytes that it receives (as well as the client address if it matches and the ara address if the alert# pin is asse rted). this is done by the client device pulling the smbus data line low after the 8th bit of each byte that is transmitted. the host will nack (not acknowledge) the data rece ived from the client by holding the smbus data line high after the 8th data bit has been sent. figure 3.1 smbus timing diagram smdata smclk t low t rise t high t fall t buf t hd:sta p s s - start condition p - stop condition t hd:dat t su:dat t su:sta t hd:sta p t su:sto s
dual rpm-based pwm fan controller datasheet smsc emc2302 13 revision 1.3 (05-18-11) datasheet 3.1.5 smbus stop bit the smbus stop bit is defined as a transition of the smbus data line from a logic ?0? state to a logic ?1? state while the smbus clock line is in a logic ?1? state. when the emc2302 detects an smbus stop bit has been communicating with the smbus protocol , it will reset its client interface and prepare to receive further communications. 3.1.6 smbus time-out the emc2302 includes an smbus timeout feature. following a 30ms period of inactivity on the smbus, the device will time-out and reset the smbus interface. the smbus timeout feature is disabled by default and can be enabled via clearing the dis_to bit in the configuration register (20h). 3.1.7 smbus and i 2 c compliance the major difference between smbus and i 2 c devices is highlighted here. for complete compliance information refer to the smbus 2.0 specification. 1. minimum frequency for smbus communications is 10khz (i 2 c has no minimum frequency). 2. the slave protocol will reset if the cl ock is held low for longer than 30ms (i 2 c has no timeout). 3. the slave protocol will reset if both the clock and data lines are held high for longer than 150us. 4. i 2 c devices do not support the alert response addre ss functionality (which is optional for smbus). 5. the block read and block write protocols are only compliant with i 2 c data formatting. they do not support smbus formatting for bl ock read and block write protocols. 3.2 smbus protocols the emc2302 is smbus 2.0 compatible and supports send byte, read byte, receive byte and write byte as valid protocols as shown below. it will re spond to the alert response address protocol but is not in full compliance. all of the below protocols use the convention in table 3.1 . when reading the protocol blocks, the value of yyyy_yyyb should be replaced with the respective smbus addresses. 3.2.1 write byte the write byte is used to write one byte of data to the registers as shown below table 3.2 . table 3.1 protocol format data sent to device data sent to the host # of bits sent # of bits sent table 3.2 write byte protocol start slave address wr ack register address ack register data ack stop 1 -> 0 yyyy_yyyb 0 0 xxh 0 xxh 0 0 -> 1
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 14 smsc emc2302 datasheet 3.2.2 read byte the read byte protocol is used to read one byte of data from the registers as shown in table 3.3 . 3.2.3 send byte the send byte protocol is used to set the internal address register pointer to the correct address location. no data is transferred during the send byte protocol as shown in ta b l e 3 . 4 . 3.2.4 receive byte the receive byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via send byte). this is used for consecutive reads of the same register as shown in ta b l e 3 . 5 . 3.2.5 block write protocol the block write is used to write multiple data byte s to a group of contiguous registers as shown in table 3.6 . it is an extension of the write byte protocol. table 3.3 read byte protocol start slave address wr ack register address ack start slave address rd ack register data nack stop 1 -> 0 yyyy_yyyb 0 0 xxh 0 0 -> 1 yyyy_yyyb 1 0 xxh 1 0 -> 1 table 3.4 send byte protocol start slave address wr ack register address ack stop 1 -> 0 yyyy_yyyb 0 0 xxh 0 0 -> 1 table 3.5 receive byte protocol start slave address rd ack register data nack stop 1 -> 0 yyyy_yyyb 1 0 xxh 1 0 -> 1 table 3.6 block write protocol start slave address wr ack register address ack register data ack 1 ->0 yyyy_yyyb 0 0 xxh 0 xxh 0 register data ack register data ack . . . register data ack stop xxh 0 xxh 0 . . . xxh 0 0 -> 1
dual rpm-based pwm fan controller datasheet smsc emc2302 15 revision 1.3 (05-18-11) datasheet 3.2.6 block read protocol the block read is used to read multiple data by tes from a group of contig uous registers as shown in table 3.7 . it is an extension of the read byte protocol. 3.2.7 alert response address the alert# output can be used as a processor interrupt or as an smbus alert when configured to operate as an interrupt. when it detects that the alert# pin is asserted, the host will send the alert response address (ara) to the general address of 0001_100xb. all devices with active interrupts will respond with their client address as shown in table 3.8 . the emc2302 will respond to the ara in the following way if the alert# pin is asserted. 1. send slave address and verify that full slav e address was sent (i.e. the smbus communication from the device was not prematurely stopped due to a bus contention event). 2. set the mask bit to clear the alert# pin. table 3.7 block read protocol start slave address wr ack register address ack start slave address rd ack register data 1->0 yyyy_yyyb 0 0 xxh 0 1 ->0 yyyy_yyyb 1 0 xxh ack register data ack register data ack register data ack . . . register data nack stop 0 xxh 0 xxh 0 xxh 0 . . . xxh 1 0 -> 1 table 3.8 alert response address protocol start alert response address rd ack device address nack stop 1 -> 0 0001_100b 1 0 yyyy_yyyb 1 0 -> 1
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 16 smsc emc2302 datasheet chapter 4 product description the emc2302 is an smbus compliant fan contro ller with two programmable frequency pwm fan drivers. the fan drivers can be operated using two modes: t he rpm-based fan speed control algorithm or the direct fan drive setting. figure 4.1 shows a system diagr am of the emc2302. 4.1 fan control modes of operation the emc2302 has two modes of operation for each fa n driver. each mode of operation uses the ramp rate control and spin up routine. 1. direct setting mode - in this mo de of operation, the user direct ly controls the fan drive setting. updating the fan driver setting register (see section 5.7 ) will instantly update the pwm fan drive. ramp rate control is optional and enabled via the en_rrc bits. ? whenever the direct setting mode is enabled, t he current drive will be changed to what was last written into the fan driver setting register. 2. fan speed control mode (fsc) - in this mo de of operation, the user determines a target tachometer count and the pwm drive setting is aut omatically updated to ac hieve this target speed. the algorithm uses the spin up routine and has user definable ramp rate controls. ? this mode is enabled setting the en_algo bit in the fan configuration register. figure 4.1 system diagram of emc2302 emc2302 smclk smdata alert# vdd 3.3v mcu tach1 tachometer pwm1 drive circuit tach2 tachometer pwm2 drive circuit 32.768khz clock input or output clk gnd
dual rpm-based pwm fan controller datasheet smsc emc2302 17 revision 1.3 (05-18-11) datasheet 4.2 pwm fan driver the emc2302 supports 2 pwm output drivers. each ou tput driver can be config ured to operate as an open-drain (default) or push-pull driver and each driver can be configured with normal or inverse polarity. additionally, the pwm frequencies are i ndependently programmable with ranges from 9.5hz to 26khz in four programmable frequency bands. 4.3 rpm-based fan speed control algorithm (fsc) the emc2302 includes 2 rpm-based fan speed control algorithms. each algorithm operates independently and controls a separate fan driver. each algorithm is controlled manually (by setting the target fan speed). this fan control algorithm uses proportional, integral, and derivative terms to automatically approach and maintain the system?s desired fan speed to an accuracy directly propor tional to the accuracy of the clock source. the desired tachometer co unt is set by the user inputting the desired number of 32.768khz cycles that occur per fan revolution. this is done by manually setting the tach target register. the user may change the target count at any time. the user may also set the target count to ffh in order to disable the fan driver for lower current operation. for example, if a desired rpm rate for a 2-pole fan is 3000 rpms, then the user would input the hexidecimal equivalent of 1296 (51h in the tach targ et register). this number represents the number of 32.768khz cycles that would occu r during the time it takes the fan to complete a single revolution when it is spinning at 3000rpms. table 4.1 fan controls active for operating mode direct setting mode fsc mode fan driver setting (read / writ e) fan driver setting (read only) edges[1:0] edges[1:0] (fan configuration) - range[1:0] (fan configuration) update[2:0] (fan configuration) update[2:0] (fan configuration) level (spin up configuration) level (spin up configuration) spinup_time[1:0] (spin up configuration) spinup_time[1:0] (spin up configuration) fan step fan step - fan minimum drive valid tach count valid tach count - tach target (read / write) tach reading tach reading - drive_fail_cnt[1:0] and drive band fail registers
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 18 smsc emc2302 datasheet the emc2302?s rpm-based fan speed control algorithm has programmable configuration settings for parameters such as ramp-rate control and spin up conditions. th e fan driver autom atically detects and attempts to alleviate a stalled/stuck fan condition while also asserting the alert# pin. the emc2302 works with fans that op erate up to 16,000 rpms and prov ide a valid tachometer signal. the fan controller will function eit her with an externally supplied 32.768khz clock source or with it?s own internal 32khz oscillator depending on the required accuracy. the emc2302 offers a clock output that enables additional devices to be slaved to the same clock source. 4.3.1 programming the rpm-based fan speed control algorithm the rpm-based fan speed control algorithm is disabled upon device power up. the following registers control the algorithm. the emc2302 fan control registers are pre-loaded with defaults that will work for a wide variety of fans so only the ta ch target register is required to set a fan speed. the other fan control registers can be used to fine-tune the algorithm behavior based on application requirements. note that steps 1 - 6 are optional and need only be performed if the default settings do not provide the desired fan response. 1. set the spin up configuration register to the spin up level and spin time desired. 2. set the fan step register to the desired step size. 3. set the fan minimum drive register to the minimum drive value that will maintain fan operation. 4. set the update time and edges options in the fan configuration register. 5. set the valid tach count register to the highest tach count that indicates the fan is spinning. refer to an17.4 rpm to tach counts conversion for examples and tables for supported rpm ranges (500, 1k, 2k, 4k). 6. set the tach target register to the desired tachometer count. 7. enable the rpm-based fan speed control algorithm by setting the en_algo bit. 4.4 tachometer measurement the tachometer measurement circ uitry is used in conjunction with the rpm-based fan speed control algorithm to update the fan driver output. addition ally, it can be used in direct setting mode as a diagnostic for host based fan control. this method monitors the tachx signal in real time. it constantly updates the tachometer measurement by reporting the number of clocks bet ween a user programmed number of edges on the tachx signal (see ta b l e 5 . 1 2 ). the tachometer measurement provides fast res ponse times for the rpm-based fan speed control algorithm and the data is presented as a count value that represents the fan rpm period. application note: the tachometer measurement method works independently of the drive settings. if the device is put into direct setting and the fan drive is set at a le vel that is lower than the fan can operate (including zero drive), then the ta chometer measurement may signal a stalled fan condition and assert an interrupt. 4.4.1 stalled fan a stalled fan is detected if the tach counter e xceeds the user-programmable valid tach count setting. if a stall is detected, the device will flag the fan as stalled and trigger an interrupt. if the rpm-based fan speed control algorithm is e nabled, the algorithm will automatically attempt to restart the fan until it detects a valid tachometer level or is disabled.
dual rpm-based pwm fan controller datasheet smsc emc2302 19 revision 1.3 (05-18-11) datasheet the fan_stall status bit indicates that a stalled fan was detected. this bi t is checked conditionally depending on the mode of operation. ? whenever the direct setting mode or the spin up routine is enabled, the fan_stall interrupt will be masked for the duration of the programmed spin up time (see ta b l e 5 . 2 2 ) to allow the fan to reach a valid speed without generating unnecessary interrupts. ? in direct setting mode, whenever the tach readin g register value exceeds the valid tach count register setting, the fan_stall status bit will be set. ? when using the rpm-based fan speed control algorithm, the stalled fan condition is checked whenever the update time is met and the fan drive setting is updated. it is not a continuous check. 4.4.2 aging fan or in valid drive detection this is useful to detect aging fan conditions (where the fan?s natural maximum speed degrades over time) or a speed setting that is faster than the f an is capable of. the emc2302 contains circuitry that detects that the programmed fan speed can be reac hed by the fan. if the tar get fan speed cannot be reached within a user defined band of tach counts at maximum drive, the drive_fail status bits are set and the alert# pin is asserted. 4.5 clk pin the clk pin has multiple functionality as determined by the settings of the configuration register. 4.5.1 external clock the emc2302 allows the user to choose between supplying an external 32.768khz clock or use of the internal 32khz oscillator to measure the tachomet er signal. this clock source is used by the rpm- based fan speed control algorithm to calculate the current fan speed. this fan controller accuracy is directly proportional to the accuracy of the clock source. when this function is used, the external clock is driven into the device via the clk pin. 4.5.2 internal clock alternately, the emc2302 may be configured to use it s internal clock as a clock output to drive other fan driver devices. when configured to operate in this mode, the device uses its internal clock for tachometer reading and drives th e clk pin using a push-pull driver. 4.6 spin up routine the emc2302 also contains programmable circuitry to control the spin up behavior of the fan driver to ensure proper fan operation. the spin up routine is initiated in direct setting mode when the setting value changes from 00h to anything else. when the fan speed control algorithm is enabled, the spin up routine is initiated under the following conditions: 1. the tach target register value changes from a value of ffh to a value that is less than the valid tach count (see section 5.15 ). 2. the rpm-based fan speed control algorithm?s m easured tach reading register value is greater than the valid tach count setting.
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 20 smsc emc2302 datasheet when the spin up routine is operating, the fan driv er is set to full scale (optional) for one quarter of the total user defined spin up time. for the remaining spin up time, the fan driver output is set at a user defined level (30% through 65% drive). after the spin up routine has finished, the em c2302 measures the tachx signal. if the measured tach reading register value is higher than the valid tach count register setting, the fan_spin status bit is set and the spin up routine will automatically attempt to restart the fan. figure 4.2 shows an example of the spin up routine in response to a programmed fan speed change based on the first condition above. 4.7 ramp rate control the fan driver can be configured with automatic ramp rate control. ramp rate control is accomplished by adjusting the drive output se ttings based on the maximum fan step register settings and the update time settings. if the rpm-based fan speed control algorithm is us ed, then this ramp rate control is automatically used. the user programs a maximum step size fo r the fan drive setting and an update time. the update time varies from 100ms to 1.6s while the fan drive maximum step can vary from 1 count to 31 counts. when a new fan drive setting is entered, the delta fr om the next fan drive setting and the previous fan drive setting is determined. if this delta is greater than the max step settings, then the fan drive setting is incrementally adjusted every 100ms to 1.6s as de termined by the update time until the target fan drive setting is reached. see figure 4.3 . figure 4.2 spin up routine 100% (optional) 30% through 65% algorithm controlled drive fan step spin up time ? of spin up time update time target count changed target count reached new target count prev target count = ffh check tach
dual rpm-based pwm fan controller datasheet smsc emc2302 21 revision 1.3 (05-18-11) datasheet 4.8 watchdog timer the emc2302 contains an internal watchdog timer for all fan drivers. the watchdog timer monitors the smbus traffic for signs of activity and works in two different modes based upon device operation. these modes are power up operation and continuous operation as described below. for either mode of operation, if fo ur (4) seconds elapse without activity detected by the host, then the watchdog will be triggered and the following will occur: 1. the watch status bit will be set. 2. the fan driver will be set to full scale drive. it will remain at full scale drive until it is disabled. 3. the alert# pin is asserted. application note: when the watchdog timer is activated, the fan speed control algorithm is automatically disabled. disabling the watchdog will not automa tically set the fan drive nor re-activate the fan speed control algorithm. this must be done manually. 4.8.1 power up operation the watchdog timer only starts immediately after po wer-up. once it has been triggered or deactivated, it will not restart although it can be configured to operate in continuous operation. while the watchdog timer is active, the device will not c heck for a stalled fan condition. figure 4.3 ramp rate control previous setting next desired setting max step max step update time update time setting changed
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 22 smsc emc2302 datasheet in the power up operation, the watchdog timer is disabled by any of the following actions: 1. writing the fan setting register will disable the watchdog timer. 2. enabling the rpm-based fan speed control algorithm by setting the en_algo bit will disable the watchdog timer. the fan driver will be set based on the rpm-based fan speed control algorithm. writing any other configuration registers will not disable the watchdog timer upon power up. 4.8.2 continuous operation when configured to operate in c ontinuous operation, the watchdog timer will start immediately. the timer will be reset by any access (read or write) to the smbus register set. the four second watchdog timer will restart upon completion of smbus activity.
dual rpm-based pwm fan controller datasheet smsc emc2302 23 revision 1.3 (05-18-11) datasheet chapter 5 register set 5.1 register map the following registers are accessible through the smbu s interface. all register bits marked as ?-? will always read ?0?. a write to these bits will have no effect. table 5.1 emc2302 register set addr r/w register name function default value lock page configuration and control 20h r/w configuration configures the clocking and watchdog functionality 40h swl page 25 24h r-c fan status stores the status bits for the rpm- based fan speed control algorithm 00h no page 26 25h r-c fan stall status stores status bits associated with a stalled fan 00h no page 26 26h r-c fan spin status stores status bits associated with a spin-up failure 00h no page 26 27h r-c drive fail status stores status bits associated with drive failure 00h no page 26 29h r/w fan interrupt enable register controls the masking of interrupts on all fan related channels 00h no page 27 2ah r/w pwm polarity config configures polarity of all pwm drivers 00h no page 28 2bh r/w pwm output config configures output type of pwm drivers 00h no page 28 2dh r/w pwm base frequency selects the base frequency for pwm output 2 00h no page 28 fan 1 control registers 30h r/w fan 1 setting always displays the most recent fan driver input setting for fan 1. if the rpm-based fan speed control algorithm is disabled, allows direct user control of the fan driver. 00h no page 29 31h r/w pwm 1 divide stores the divide ratio to set the frequency for fan 1 01h no page 30 32h r/w fan 1 configuration 1 sets configuration values for the rpm- based fan speed control algorithm for the fan 1 driver 2bh no page 30 33h r/w fan 1 configuration 2 sets additional configuration values for the fan 1 driver 28h swl page 32
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 24 smsc emc2302 datasheet 35h r/w gain 1 holds the gain terms used by the rpm- based fan speed control algorithm for the fan 1 driver 2ah swl page 33 36h r/w fan 1 spin up configuration sets the configuration values for spin up routine of the fan 1 driver 19h swl page 34 37h r/w fan 1 max step sets the maximum change per update for the fan 1 driver 10h swl page 35 38h r/w fan 1 minimum drive sets the minimum drive value for the fan 1 driver 66h (40%) swl page 36 39h r/w fan 1 valid tach count holds the tachometer reading that indicates fan 1 is spinning properly f5h swl page 36 3ah r/w fan 1 drive fail band low byte stores the number of tach counts used to determine how the actual fan speed must match the target fan speed at full scale drive 00h swl page 37 3bh r/w fan 1 drive fail band high byte 00h swl 3ch r/w tach 1 target low byte holds the target tachometer reading low byte for fan 1 f8h no page 37 3dh r/w tach 1 target high byte holds the target tachometer reading high byte for fan 1 ffh no page 37 3eh r tach 1 reading high byte holds the tachometer reading high byte for fan 1 ffh no page 38 3fh r tach 1 reading low byte holds the tachometer reading low byte for fan 1 f8h no page 38 fan 2 control registers 40h r/w fan 2 setting always displays the most recent fan driver input setting for fan 2. if the rpm-based fan speed control algorithm is disabled, allows direct user control of the fan driver. 00h no page 29 41h r/w pwm 2 divide stores the divide ratio to set the frequency for fan 2 01h no page 30 42h r/w fan 2 configuration1 sets configuration values for the rpm- based fan speed control algorithm for fan 2 2bh no page 30 43h r/w fan 2 configuration 2 sets additional configuration values for the fan 2 driver 28h swl page 32 45h r/w gain 2 holds the gain terms used by the rpm- based fan speed control algorithm for fan 2 2ah swl page 33 46h r/w fan 2 spin up configuration sets the configuration values for spin up routine of the fan 2 driver 19h swl page 34 47h r/w fan 2 max step sets the maximum change per update for fan 2 10h swl page 35 table 5.1 emc2302 regi ster set (continued) addr r/w register name function default value lock page
dual rpm-based pwm fan controller datasheet smsc emc2302 25 revision 1.3 (05-18-11) datasheet during power-on-reset (por), the default values are stored in the registers. a por is initiated when power is first applied to the part and the vo ltage on the vdd supply surpasses the por level as specified in the electrical charac teristics. any reads to undefined registers will return 00h. writes to undefined registers will not have an effect. 5.1.1 lock entries the lock column describes the locking mechanism, if any, used for individual registers. all swl registers are software locked and therefore made read-only when the lock bit is set. 5.2 configuration register 48h r/w fan 2 minimum drive sets the minimum drive value for the fan 2 driver 66h (40%) swl page 36 49h r/w fan 2 valid tach count holds the tachometer reading that indicates fan 2 is spinning properly f5h swl page 36 4ah r/w fan 2 drive fail band low byte stores the number of tach counts used to determine how the actual fan speed must match the target fan speed at full scale drive 00h swl page 37 4bh r/w fan 2 drive fail band high byte 00h swl 4ch r/w tach 2 target low byte holds the target tachometer setting low byte for fan 2 f8h no page 37 4dh r/w tach 2 target high byte holds the target tachometer setting high byte for fan 2 ffh no page 37 4eh r tach 2 reading high byte holds the tachometer reading high byte for fan 2 ffh no page 38 4fh r tach 2 reading low byte holds the tachometer reading low byte for fan 2 f8h no page 38 lock register ef r/w software lock locks all swl registers 00h swl page 39 revision registers fdh r product id stores the unique product id 36h no page 39 feh r manufacturer id stores the manufacturer id 5dh no page 40 ffh r revision revision 80h no page 40 table 5.2 configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 20h r/w configuration mask dis_to wd_en - - - dr_ext_ clk use_ ext_ clk 40h table 5.1 emc2302 regi ster set (continued) addr r/w register name function default value lock page
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 26 smsc emc2302 datasheet the configuration register controls the basic f unctionality of the emc2302. the bits are described below. the configuration register is software locked. bit 7 - mask - blocks the aler t# pin from being asserted. ? ?0? (default) - the alert# pin is unmasked. if any bit in the status registers is set, the alert# pin will be asserted (unless individually masked via the fan interrupt enable register). ? ?1? - the alert# pin is masked and will not be asserted. bit 6 - dis_to - disables the smbus timeout function for the smbus client (if enabled). ? ?0? - the smbus timeout function is enabled. ? ?1? (default) - the smbus timeout function is disabled allowing the device to be fully i 2 c compliant. bit 5 - wd_en - enables the watchdog timer (see section 4.8 ) to operate in continuous mode. ? ?0? (default) - the watchdog timer does not operate continuously. it will function upon power up and at no other time (see section 4.8.1 ). ? ?1? - the watchdog timer operates continuously as described in section 4.8.2 . bit 1 - dr_ext_clk - enables the internal tachometer clock to be driven out on the clk pin so that multiple devices can be synced to the same source. ? ?0? (default) - the clk pin acts as a clock input. ? ?1? - the clk pin acts as a clock output and is a push-pull driver. bit 0 - use_ext_clk - enables the emc2302 to use a clock present on the clk pin as the tachometer clock. if the dr_ext_clk bit is set, then this bit is ignored and the device will use the internal oscillator. ? ?0? (default) - the emc2302 will use its internal oscillator for all tachometer measurements. ? ?1? - the emc2302 will use the oscillator pr esented on the clk pin for all tachometer measurements. 5.3 fan status registers the fan status registers contain the stat us bits associated with each fan driver. 5.3.1 fan status - 24h the fan status register indicates t hat one or both of the fan drivers has stalled or failed or that the watchdog timer has expired (see section 4.8 ). table 5.3 fan status registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 24h r-c fan status watch - - - - drive_ fail fan_ spin fan_ stall 00h 25h r-c fan stall status - - - - - - fan2_ stall fan1_ stall 00h 26h r-c fan spin status - - - - - - fan2_ spin fan1_ spin 00h 27h r-c fan drive fail status ----- - drive_ fail2 drive_ fail1 00h
dual rpm-based pwm fan controller datasheet smsc emc2302 27 revision 1.3 (05-18-11) datasheet bit 7 - watch - indicates that the watchdog timer has expired. when set, each fan is driven to 100% duty cycle and will remain at 100% duty cycle until they are programmed. this bit is cleared when it is read. bit 2 - drive_fail - indicates that one or both fan drivers cannot meet the programmed fan speed at maximum pwm duty cycle. this bit is set when any bit in the fan dr ive fail status register is set and cleared when all bits in the fan dr ive fail status register are cleared. bit 1 - fan_spin - indicates that one or both fan drivers cannot spin up. this bit is set when any bit in the fan spin status register is set and cleared w hen all of the bits in th e fan spin status register are cleared. bit 0 - fan_stall - indicates that one or both fan drivers have stalled. this bit is set when any bit in the fan stall status register is set and cleared when all of the bits in the fan stall status register are cleared. 5.3.2 fan stall status - 25h the fan stall status register indicates which fan driver has detected a stalled condition (see section 4.4.1 ). all bits are cleared upon a read if the error condition has been removed. bit 1 - fan2_stall - indicates that fan 2 has stalled. bit 0 - fan1_stall - indicates that fan 1 has stalled. 5.3.3 fan spin status - 26h the fan spin status register indicates wh ich fan driver has failed to spin-up (see section 4.6 ). all bits are cleared upon a read if the error condition has been removed. bit 1 - fan2_spin - indicates that fan 2 has failed to spin up. bit 0 - fan_spin - indicates that fan 1 has failed to spin up. 5.3.4 fan drive fail status - 27h the fan drive fail status register indicates whic h fan driver cannot drive to the programmed speed even at 100% duty cycle (see section 4.4.2 and section 5.12 ). all bits are cleared upon a read if the error condition has been removed. bit 1 - drive_fail2 - indicates that fan 2 cannot reach its programmed fan speed even at 100% duty cycle. this may be due to an aging fan or invalid programming. bit 0 - drive_fail1 - indicates that fan 1 cannot reach its programmed fan speed even at 100% duty cycle. this may be due to an aging fan or invalid programming. 5.4 fan interrupt enable register the fan interrupt enable controls the masking for each fan channel. when a channel is enabled, it will cause the alert# pin to be asserted when an error condition is detected. table 5.4 fan interrupt enable register addrr/wregisterb7b6b5b4 b3 b2 b1b0default 29h r/w fan interrupt enable ---- - - fan2_ int_en fan1_ int_en 00h
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 28 smsc emc2302 datasheet bit 1 - fan2_int_en - allows fan 2 to assert the alert# pin if an error is detected. bit 0 - fan1_int_en - allows fan 1 to assert th e alert# pin if an error condition is detected. ? ?0? (default) - an error condition on fan x will no t cause the alert# pin to be asserted, however the status registers will be updated normally. ? ?1? - an error condition (stall, spin up, drive fail) on fan x will cause the alert# pin to be asserted. 5.5 pwm configuration registers the pwm config registers control the outpu t type and polarity of all pwm outputs. 5.5.1 pwm polarity config - 2ah bit 1 - polarity2 - determines the polarity of pwm 2. bit 0 - polarity1 - determines the polarity of pwm 1. ? ?0? (default) - the polarity of the pwm driver is normal. a drive setting of 00h will cause the output to be set at 0% duty cycle and a drive setting of ffh will cause th e output to be set at 100% duty cycle. ? ?1? - the polarity of the pwm driver is inverted. a drive setting of 00h will cause the output to be set at 100% duty cycle and a drive setting of ffh will cause the ou tput to be set at 0% duty cycle. 5.5.2 pwm output config - 2bh bit 1 - pwm2_ot - determines the output type of pwm 2 driver. bit 0 - pwm1_ot - determines the output type of the pwm 1 driver. ? ?0? (default) - the pwm 1 output is configured as an open drain output. ? ?1? - the pwm 1 output is conf igured as a push-pull output. 5.6 pwm base frequency register table 5.5 pwm configuration registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 2ah r/w pwm polarity config --- - - - polarity 2 polarity 1 00h 2bh r/w pwm output config - - - - - - pwm2_ot pwm1_ot 00h table 5.6 pwm base frequency register addrr/wregisterb7b6b5b4b3b2b1b0default 2dh r/w pwm base frequency ---- pwm_ base 2_1 pwm_ base 2_0 pwm_ base 1_1 pwm_ base 1_0 00h
dual rpm-based pwm fan controller datasheet smsc emc2302 29 revision 1.3 (05-18-11) datasheet the pwm base frequency register determines the base frequency that is used with the pwm divide register to determine the final pw m frequency. each pwm frequency is set by the base frequency and its respective divide ratio (see section 5.8 ). controls the base frequency of pwm drivers 1-3 2 bits 3-2 - pwm_base2[1:0] - determines the base frequency of the pwm2 driver. bits 1-0 - pwm_base1[1:0] - determines the base frequency of the pwm1 driver. 5.7 fan setting registers the fan setting register always displays the current setting of the respective fan driver. reading from any of the registers will report the current fan speed setting of the appropriate fan driver regardless of the operating mode. therefore it is possible that reading from this re gister will not report data that was previously written into this register. while the rpm-based fan speed control algorithm is active, the register is read only. writing to the register will have no effect and the data will not be stored. the contents of the register repr esent the weighting of each bit in determining the final output voltage. the output drive for a pwm output is given by equation [1] . table 5.7 pwm_ba sex[1:0] bit decode pwm_basex[1:0] base frequency 10 0 0 26.00khz (default) 0 1 19.531khz 1 0 4,882hz 1 1 2,441hz table 5.8 fan driver setting registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 30h r/w fan 1 setting 128 64 32 16 8 4 2 1 00h 40h r/w fan 2 setting 128 64 32 16 8 4 2 1 00h [1] drive value 255 -------------------- - ?? ?? 100% =
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 30 smsc emc2302 datasheet 5.8 pwm divide registers the pwm divide registers determine the final frequency of the respective pwm fan driver. each driver base frequency is divided by the value of the respec tive pwm divide register to determine the final frequency. the duty cycle settings are not affected by these settings, only the final frequency of the pwm driver. a value of 00h will be decoded as 01h. 5.9 fan configuration 1 registers the fan configuration 1 registers control the gener al operation of the rpm-based fan speed control algorithm used for the respective fan driver. bit 7 - en_algox - enables the rpm-based fan speed control algorithm. ? ?0? - (default) the control circuitry is disabled and the fan driver output is determined by the fan driver setting register. ? ?1? - the control circuitry is enabled and the fa n driver output will be automatically updated to maintain the programmed fan speed as indicated by the tach target register. bits 6- 5 - rangex[1:0] - adjusts the range of re ported and programmed tac hometer reading values. the range bits determine the weighting of all tach values (including the valid tach count, tach target, and tach reading) as shown in ta b l e 5 . 11 . table 5.9 pwm divide registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 31h r/w fan 1 divide 128 64 32 16 8 4 2 1 01h 41h r/w fan 2 divide 128 64 32 16 8 4 2 1 01h table 5.10 fan configuration 1 registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 32h r/w fan 1 configuration 1 en_ algo1 range1[1:0] edges1[1:0] update1[2:0] 2bh 42h r/w fan 2 configuration 1 en_ algo2 range2[1:0] edges2[1:0] update2[2:0] 2bh table 5.11 range decode rangex[1:0] reported minimum rpm tach count multiplier 10 005001 0 1 1000 (default) 2 1 0 2000 4 1 1 4000 8
dual rpm-based pwm fan controller datasheet smsc emc2302 31 revision 1.3 (05-18-11) datasheet bits 4-3 - edgesx[1:0] - determines the minimum number of edges that must be detected on the tachx signal to determine a single rotation. a ty pical fan measured 5 edges (for a 2-pole fan). for more accurate tachometer measurement, the minimum number of edges measured may be increased. increasing the number of edges m easured with respect to the number of poles of the fan will cause the tach reading registers to indicate a fan speed that is higher or lowe r than the actual speed. in order for the fsc algorithm to operate correctly, the tach target must be updated by the user to accommodate this shift. the effective tach multiplier shown in ta b l e 5 . 1 2 is used as a direct multiplier term that is applied to the actual rpm to achieve the reported rpm. it should only be applied if the number of edges measured does not match the numbe r of edges expected based on the number of poles of the fan (which is fixed for any given fan). contact smsc for recommended settings when us ing fans with more or less than 2 poles. bit 2-0 - updatex[2:0] - determines the base time between fan driver updates. the update time, along with the fan step register, is used to control the ramp rate of the drive response to provide a cleaner transition of the actual fan operation as the desired fan speed changes. the update time is set as shown in table 5.13 . table 5.12 minimum edges for fan rotation edgesx[1:0] minimum tach edges number of fan poles effective tach multiplier (based on 2 pole fans) 10 0 0 3 1 pole 0.5 0 1 5 2 poles (default) 1 1 0 7 3 poles 1.5 1 1 9 4 poles 2 table 5.13 update time updatex[2:0] update time 21 0 00 0 100ms 00 1 200ms 01 0 300ms 0 1 1 400ms (default) 10 0 500ms 10 1 800ms 1 1 0 1200ms 1 1 1 1600ms
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 32 smsc emc2302 datasheet 5.10 fan configuration 2 registers the fan configuration 2 register control the tachometer measuremen t and advanced features of the rpm-based fan speed control algorithm. bit 6 - en_rrcx - enables ramp rate control when the corresponding fan driver is operated in the direct setting mode. ? ?0? (default) - ramp rate control is disabled. when the fan driv er is operating in direct setting mode, the fan setting will instantly transitio n to the next programmed setting. ? ?1? - ramp rate control is enabled. when the fan driver is operating in direct setting mode, the fan drive setting will follow the ramp rate controls as determined by the fan step and update time settings. the maximum fan drive setting step is capped at the fan step setting and is updated based on the update time as given by table 5.13 . bit 5 - glitch_enx - disables the low pass glitch filter that removes high frequency noise injected on the tachx pin. ? ?0? - the glitch filter is disabled. ? ?1? (default) - the glit ch filter is enabled. bits 4 - 3 - der_optx[1:0] - control some of the adv anced options that affect the derivative portion of the rpm-based fan speed c ontrol algorithm as shown in ta b l e 5 . 1 5 . table 5.14 fan configuration 2 registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 33h r/w fan 1 configuration 2 - en_ rrc1 glitch_ en1 der_opt1 [1:0] err_rng1[1:0] - 28h 43h r/w fan 2 configuration 2 - en_ rrc2 glitch_ en2 der_opt2 [1:0] err_rng2[1:0] - 28h table 5.15 deri vative options der_optx[1:0] operation 10 0 0 no derivative options used 01 basic derivative. the derivative of the error from the current drive setting and the target is added to the iterative fan driv e register setting (in addition to proportional and integral terms) (default) 10 step derivative. the derivative of the error from the current drive setting and the target is added to the iterative fan drive register setting and is not capped by the fan step register. 11 both the basic derivative and the step derivative are used effectively causing the derivative term to have double the effect of the derivative term.
dual rpm-based pwm fan controller datasheet smsc emc2302 33 revision 1.3 (05-18-11) datasheet bit 2 - 1 - err_rngx[1:0] - control some of the adv anced options that affect the error window. when the measured fan speed is within the programmed error window around the target speed, then the fan drive setting is not updated. the algorithm will continue to monitor the fan speed and calculate necessary drive setting changes based on the error; however, these changes are ignored. 5.11 gain registers the gain registers store the gain terms used by the proportional and integral po rtions of each of the rpm-based fan speed control algorithms. these gain terms are used as the kd, ki, and kp gain terms in a classic pid control solution. bits 5 - 4 - gaindx[1:0] - controls the derivativ e gain term used by the fsc algorithm as shown in table 5.18 . bits 3-2 - gainix[1:0] - controls the integral gain term used by the fsc algorithm as shown in table 5.18 . bits 1-0 - gainp[1:0] - controls the proportional gain term used by the fsc algorithm as shown in table 5.18 . table 5.16 error range options err_rngx[1:0] operation 10 0 0 0 rpm (default) 0 1 50 rpm 1 0 100 rpm 1 1 200 rpm table 5.17 gain registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 35h r/w gain 1 register - - gaind1[1:0] gaini1[1:0] gainp1[1:0] 2ah 45h r/w gain 2 register - - gaind2[1:0] gaini2[1:0] gainp2[1:0] 2ah table 5.18 gain decode gaind or gainp or gaini [1:0] respective gain factor 10 00 1x 01 2x 1 0 4x (default)
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 34 smsc emc2302 datasheet 5.12 fan spin up configuration registers the fan spin up configuration registers control t he settings of spin up routine. the fan spin up configuration registers are software locked. bit 7 - 6 - drive_fail_cnt x[1:0] - determines how many update cycles are used for the drive fail detection function as shown in ta b l e 5 . 2 0 . this circuitry determines whether the fan can be driven to the desired tach target. bit 5 - nokickx - determines if t he spin up routine will drive the fan to 100% duty cycle for 1/4 of the programmed spin up time before driving it at the programmed level. ? ?0? (default) - the spin up routine will drive the fa n driver to 100% for 1/4 of the programmed spin up time before re verting to the programmed spin level. ? ?1? - the spin up routine will not drive the fan driver to 100%. it will set the drive at the programmed spin level for the entire dur ation of the programmed spin up time. bits 4 - 2 - spin_lvlx[2:0] - determines the final dr ive level that is used by the spin up routine as shown in ta b l e 5 . 2 1 . 11 8x table 5.19 fan spin up configuration registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 36h r/w fan 1 spin up configuration drive_fail_ cnt1 [1:0] nokick1 spin_lvl1[2:0] spinup_time 1 [1:0] 19h 46h r/w fan 2 spin up configuration drive_fail_ cnt2 [1:0] nokick2 spin_lvl2[2:0] spinup_time 2 [1:0] 19h table 5.20 drive_fail_cnt[1:0] bit decode drive_fail_cntx[1:0] number of update periods 10 0 0 disabled - the drive fail detect ion circuitry is disabled (default) 01 16 - the drive fail detection circuitry will count for 16 update periods 10 32 - the drive fail detection circuitry will count for 32 update periods 11 64 - the drive fail detection circuitry will count for 64 update periods table 5.18 gain decode (continued) gaind or gainp or gaini [1:0] respective gain factor 10
dual rpm-based pwm fan controller datasheet smsc emc2302 35 revision 1.3 (05-18-11) datasheet bit 1 -0 - spinup_timex[1:0] - determines the maximu m spin time that the spin up routine will run for (see section 4.6 ). if a valid tachometer measurement is not detected before the spin time has elapsed, an interrupt will be generated. when the rpm-based fan speed control algorithm is active, the fan driver will attempt to re-start the fan immedi ately after the end of the last spin up attempt. the spin time is set as shown in ta b l e 5 . 2 2 . 5.13 fan max step registers table 5.21 spin level spin_lvlx[2:0] spin up drive level 210 0 0 0 30% 0 0 1 35% 0 1 0 40% 0 1 1 45% 1 0 0 50% 1 0 1 55% 1 1 0 60% (default) 1 1 1 65% table 5.22 spin time spinup_timex[1:0] total spin up time 10 0 0 250 ms 0 1 500 ms (default) 1 0 1 sec 1 1 2 sec table 5.23 fan max step registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 37h r/w fan 1 max step - - 32 16 8 4 2 1 10h 47h r/w fan 2 max step - - 32 16 8 4 2 1 10h
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 36 smsc emc2302 datasheet the fan max step registers, along with the update time, control the ramp rate of the fan driver response calculated by the rpm-based fan speed control algorithm. the value of the register represents the maximum step size each fan driver will take between update times (see section 5.9 ). when the fsc algorithm is enabled, ramp rate cont rol is automatically us ed. when the fsc is not active, then ramp rate control can be ena bled by asserting the en_rrc bit (see section 5.10 ). application note: the update bits and fan step register se ttings operate independently of the rpm-based fan speed control algorithm and will always limit the fan drive setting. that is, if the programmed fan drive setting (e ither as determined by the rpm-based fan speed control algorithm or by manual settings) exceeds the cu rrent fan drive setting by greater than the fan step register setting, the emc2302 will li mit the fan drive change to the value of the fan step register. it will use the update time to determine how often to update the drive settings. application note: if the fan speed control algorithm is used, t he default settings in the fan configuration 2 register will cause the maximum fan step settings to be ignored. the fan max step registers are software locked. 5.14 fan minimum drive registers the fan minimum drive registers store the minimum drive setting for each rpm-based fan speed control algorithm. the rpm-based fan speed control algorithm will not drive the fan at a level lower than the minimum drive unless the target fan speed is set at ffh (see section 5.17 ). during normal operation, if the fan stops for any reason (including low drive), the rpm-based fan speed control algorithm will attempt to restart the fan. setting the fan minimum drive register to a setting that will maintain fan operat ion is a useful way to avoid potent ial fan oscillations as the control circuitry attempts to drive it at a level that cannot support fan operation. the fan minimum drive registers are software locked. 5.15 valid tach count registers table 5.24 minimum fan drive registers addrr/w registerb7b6b5b4b3b2b1b0default 38h r/w fan 1 minimum drive 128643216 8 4 2 1 66h (40%) 48h r/w fan 2 minimum drive 128643216 8 4 2 1 66h (40%) table 5.25 valid tach count registers addrr/wregisterb7b6b5b4b3b2b1b0default 39h r/w valid tach count 1 4096 2048 1024 512 256 128 64 32 f5h 49h r/w valid tach count 2 4096 2048 1024 512 256 128 64 32 f5h
dual rpm-based pwm fan controller datasheet smsc emc2302 37 revision 1.3 (05-18-11) datasheet the valid tach count registers store the maximum tach reading register value to indicate that each fan is spinning properly. the value is referenced at the end of the spin up routine to determine if the fan has started operating and deci de if the device needs to retry. see equation [2] in section 5.18 for translating the count to an rpm. if the tach reading register value exceeds the valid tach count register (indicating that the fan rpm is below the threshold set by this count), then a stalled fan is detected. in this condition, the algorithm will automatically begin its spin up routine. if a tach target setting is set above the valid tach count setting, then that setting will be ignored and the algorithm will use the current fan drive setting. the valid tach count registers are software locked. 5.16 fan drive fail band registers the fan drive fail band registers store the num ber of tach counts used by the fan drive fail detection circuitry. this circuitry is activated when the fan drive setting high byte is at ffh. when it is enabled, the actual measured fan speed is compar ed against the target fan speed. these registers are only used when the fsc is active. this circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually capable of reaching. if the measured fan speed does not exceed the target fan speed minus the fan drive fail band register settings for a period of time longer than set by the drive_fail_cntx[1:0] bits, then the drive_fail status bit wil l be set and an interrupt generated. 5.17 tach target registers table 5.26 fan drive fail band registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 3ah r/w fan 1 drive fail band low byte 16 8 4 2 1 - - - 00h 3bh r/w fan 1 drive fail band high byte 4096 2048 1024 512 256 128 64 32 00h 4ah r/w fan 2 drive fail band low byte 16 8 4 2 1 - - - 00h 4bh r/w fan 2 drive fall band high byte 4096 2048 1024 512 256 128 64 32 00h table 5.27 tach target registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 3ch r/w tach target 1 low byte 168421 - - - f8h 3dh r/w tach target 1 high byte 4096 2048 1024 512 256 128 64 32 ffh
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 38 smsc emc2302 datasheet the tach target registers hold the target tachom eter value that is maintained by the rpm-based fan speed control algorithm. the value in the tach target registers will a lways reflect the current tach target value. if one of the algorithms is enabled, setting the tach target register to ffh will disable the fan driver (set the fan drive setting to 0%). setting the tach target to any other value (from a setting of ffh) will cause the algorithm to invoke the spin up routine after which it will function normally. the tach target is not applied until the high byte is written. once the high byte is written, the current value of both high and low bytes will be used as the next tach target. 5.18 tach reading registers the tach reading registers? contents describe the current tachometer reading for each of the fans. by default, the data represents the fan speed as the number of 32khz clock periods that occur for a single revolution of the fan. equation [2] shows the detailed conversion from tach measurement (count) to rpm while equation [3] shows the simplified translation of tach readin g register count to rpm assuming a 2-pole fan, measuring 5 edges, with a frequency of 32.768khz. these equations ar e solved and tabulated for ease of use in an17.4 rpm to tach counts conversion . whenever the high byte register is read, the corresponding low byte data will be loaded to internal shadow registers so that when the low byte is r ead, the data will always coincide with the previously read high byte. 4ch r tach target 2 low byte 168421 - - - f8h 4dh r/w tach target 2 high byte 4096 2048 1024 512 256 128 64 32 ffh table 5.28 tach reading registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 3eh r fan 1 tach 4096 2048 1024 512 256 128 64 32 ffh 3fh r fan 1 tach low byte 168421 - - - f8h 4eh r fan 2 tach 4096 2048 1024 512 256 128 64 32 ffh 4fh r fan 2 tach low byte 168421 - - - f8h table 5.27 tach target registers (continued) addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default
dual rpm-based pwm fan controller datasheet smsc emc2302 39 revision 1.3 (05-18-11) datasheet 5.19 software lock register the software lock register controls the software locking of critical re gisters. this register is software locked. bit 0 - lock - this bit acts on all registers that ar e designated swl. when this bit is set, the locked registers become read on ly and cannot be updated. ? ?0? (default) - all swl registers can be updated normally. ? ?1? - all swl registers cannot be updated and a hard-reset is required to unlock them. 5.20 product id register the product id register contains a unique 8-bit word that identifies the product. where: [2] poles = number of poles of the fan (typically 2) f tach = the tachometer measurement frequen cy (typically 32.768khz) n = number of edges measured (typically 5 for a 2 pole fan) m = the multiplier defined by the range bits [3] count = tach reading register value (in decimal) table 5.29 software lock register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default efh r/w software lock --- ----lock00h table 5.30 product id register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default fdh r product id 0 0 1 1 0 1 1 0 36h rpm 1 poles () -------------------- n 1 ? () count 1 m ---- - --------------------------------- - f tach 60 = rpm 3,932,160 m count -------------------------------------- =
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 40 smsc emc2302 datasheet 5.21 manufacturer id register the manufacturer id register contains an 8-bit word that identifies smsc. 5.22 revision register the revision register contains an 8-bit word that identifies the die revision. table 5.31 manufacturer id register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default feh r manufacturer id 0 1 0 1 1 1 0 1 5dh table 5.32 revision register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default ffh r revision 1 0 0 0 0 0 0 0 80h
dual rpm-based pwm fan controller datasheet smsc emc2302 41 revision 1.3 (05-18-11) datasheet chapter 6 typical operating curves the following typical operating curves are included. ? supply current vs. temperature ? supply current vs. supply voltage ? fan tach accuracy vs. temperature ? fan tach accuracy vs. supply voltage ? pwm output frequency vs. supply voltage ? pwm output frequency vs. temperature ? fsc operation supply current vs. ambient temperature 250 300 350 400 450 500 -50 0 50 100 150 temperature (c) supply current (ua) supply current (ua) ambient temperature (c) supply current vs. supply voltage 250 300 350 400 450 500 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 supply voltage (v) supply current (ua) supply current (ua) supply voltage (v) tachometer measurement accuracy vs. ambient temperature -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -50 0 50 100 150 temperautre (c) tach measurement accuracy (% ambient temperature (c) tach measurement accuracy (%) tachometer measurement accuracy vs. supply voltage -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 supply voltage (v) tach measurement accuracy (% tach measurement accuracy (%)
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 42 smsc emc2302 datasheet pwm frequency vs. ambient temperature v dd = 3.3v, base frequncy = 26khz 25000 25200 25400 25600 25800 26000 26200 26400 26600 26800 27000 -50 0 50 100 150 temperature ( c) ambient temperature (c) pwm frequency (hz) pwm frequency vs. supply voltage ta = 25c, base frequncy = 26khz 25000 25200 25400 25600 25800 26000 26200 26400 26600 26800 27000 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 supply voltage (v) pwm frequency (hz) pwm output 10x zoom on pwm output spin time = 1.0s; spin level = 55%; updated time = 200ms; rpm target from 0 rpm -> 8000 rpm @ time t = 0 fsc algorithm spin up routine t = 0 duty cycle measured = 53.8% pwm output 10x zoom on pwm output spin time = 1.0s; spin level = 50%; updatetime = 200ms; rpm target from 0 rpm -> 8000 rpm @ time t = 0 fsc algorithm spin up routine ? nokick t = 0 duty cycle measured = 50% pwm output 10x zoom on pwm output update time = 200ms; max step = 16 pwm counts rpm target from 0 rpm -> 8000 rpm @ time t = 0 fsc algorithm pwm ramping spin up routine ends ? begins normal operation update time ends, pwm duty cycle changed update time ends, pwm duty cycle changed duty cycle measured
dual rpm-based pwm fan controller datasheet smsc emc2302 43 revision 1.3 (05-18-11) datasheet chapter 7 package drawing 7.1 emc2302 package information figure 7.1 emc2302 package drawing - 10-pin msop a a2 a1 se ating pl ane side view ccc c gauge plane h 3-d view top view c 3 2 end view 4 3 5 detail "a" no te s: 1 . al l di mensions are in milli meter. 2 . tol erance on the true position of e ach lead is 0.0 4 mm at ma ximum material condition. 3. package body dimensi ons "d" and "e1" do not incl ude mold/interlea d protrusions or flash. maximum mol d protrusions or fla sh i s 0. 15 mm (0.0 06 inches) per end a nd side. dime nsions "d" and "e1" are de te rmined at the oute rmos t e xtreme s of the pl astic b ody, i ncl uding a ny misma tch be tween top and bottom pla sti c body. they are de te rmi ned at datum pl ane "h". 4 . dimens ions "b" and "c" apply to the flat se ction of the lead betwee n 0 .08 mm and 0.15 mm from the l ead tip. 5. details of the p in 1 identifier a re op tional, but must be located withi n the zone in dic at ed. a i n i ti a l r el e ase 3 / 29 / 05 s. k. i l i e v c see detail "a" e d e1 e pi n 1 identi fier area (d/2 x e1/2) 10 x b l (0.95) 0.25 0 - 8 di m a nd t ol pe r as me y14.5m - 19 94 fi nish ma terial decim al x.x x.xx x.xxx 8 0 a r ka y d r i ve hauppauge, ny 11 788 usa an g u l ar pr i n t w it h "s ca le to fi t" d o n o t s c ale d ra wi n g ch ecked appr oved name drawn dwg num ber sc ale title dat e std compliance unless otherw ise spe cified dim ensi ons are in millimeters and t olerances are: thir d ang l e pro j ection rev sheet revision descriptio n revisio n history released by date package outline 10 pin ts so p, 3x3 mm bo dy, 0.5 0 mm pitch 1 - - 0.1 0.05 0.025 s.k.il iev s.k.il iev s.k.il iev 3/29 /0 5 3/29 /0 5 1:1 3/29 /0 5 mo-10-tssop-3x3 jedec : mo-187 1 of 1 a c sea ti ng p lane 4
dual rpm-based pwm fan controller datasheet revision 1.3 (05-18-11) 44 smsc emc2302 datasheet 7.2 package markings figure 7.2 emc2302 package markings bottom line: 1-t ? device number line: 2-t version, revision, country code (vrcc) all top lines center horizontal alignment pb-free/green symbol (matte sn) 2x 1.5pt top e3 pin 1 line: 1-b ? date code (yyww) line: 2-b ? first 3 digits of lot number 3x 1.5pt pin 1 line: 3-b ? last 4 digits of lot number 23 02 vr cc yyww 123 456a
dual rpm-based pwm fan controller datasheet smsc emc2302 45 revision 1.3 (05-18-11) datasheet chapter 8 datasheet revision history table 8.1 customer revision history revision level & date secti on/figure/entr y correction rev. 1.3 (05-18-11) section 4.8, "watchdog timer" the alert# pin is asserted when the watchdog is triggered. section 5.2, "configuration register" corrected description fo r mask bit. changed ?if any bit in either status register is set, the alert# pins will be asserted (unless individually masked via the mask register)? to ?if any bit in the status registers is set, the alert# pin will be asserted (unless individually masked via the fan interrupt enable register)?. rev. 1.2 (03-22-10) table 2.3, "smbus electrical specifications" updated smbus data hold time spec to 0 us rev. 1.1 (10-12-09) table 2.2, "electrical specifications" tachometer setting accuracy max was changed from +/-3% to +/-2%. chapter 6, typical operating curves added typical operating curves ordering information added emc2302-2 for 2nd smbus address rev. 1.0 (05-15-09) initial release of datasheet

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